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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
Rev. 04 -- 15 January 2009 Product data sheet
1. General description
The TDA9984A is a High-Definition Multimedia Interface (HDMI) v. 1.3 transmitter with embedded 1080p upscaling functionality. It is backward compatible DVI 1.0 and can be connected to any DVI 1.0 and HDMI sink. It allows mixing a 3 x 8-bit RGB or YCbCr video stream with a pixel rate up to 150 MHz together with up to 4 x I2S-bus or one S/PDIF audio streams with an audio sampling rate up to 192 kHz. It supports Gamut boundary description (xvYCC), as well as HD audio, both HDMI 1.3 features. A programmable upscaling block allows creating a 1080p output from a standard definition input. An intrafield deinterlacer is included in the scaler. In order to be compatible with most applications, and thanks to the integration of a fully programmable input formatter and color space conversion block, the video input formats accepted also include YCbCr 4 : 4 : 4 (up to 3 x 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 x 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 x 12-bit). In case of ITU656-like format, the input pixel clock can be made active on both edges. The TDA9984A includes a HDCP 1.2 compliant cipher block. The HDCP key are stored internally in a non-volatile OTP memory for maximum security. The TDA9984A includes a true I2C-bus master interface for DDC-bus communication for EDID purpose and HDCP purpose. The TDA9984A can be controlled by an I2C-bus interface.
2. Features
I 3 x 8-bit video data input buses; CMOS and LV-TTL compatible I Horizontal synchronization, vertical synchronization and data enable inputs or VREF, HREF and FREF inputs which can be used for synchronization I Pixel rate clock input can be made active on one or both edges; selectable via I2C-bus I 4 x I2S-bus audio input channels, one S/PDIF channel; audio data rate up to 192 kHz per input for both standards I Dolby-True HD and DTS-HD High bit rate audio support through the use of the HBR interface I 250 MHz to 1.50 GHz TMDS transmitter operation I Programmable input formatter and upsampler/interpolator allows input of any of the 4 : 4 : 4 or 4 : 2 : 2 semi-planar and 4 : 2 : 2 ITU656-like formats
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
I Programmable color space converter allows to input RGB video data and to output RGB or YCbCr 4 : 2 : 2 HDMI video data, or to input YCbCr video data and to output RGB or YCbCr 4 : 2 : 2 HDMI video data; converter can be passed I Upscaler allows creating a 1080p output from a standard definition input by using intelligent edge interpolation I Repetition of video samples as required by the HDMI standard I Insertion of HDMI additional information such as InfoFrames I Color gamut metadata packet transmission (xvYCC) I Downstream availability using hot plug detection (HPD input) and receiver detection (RxSense circuit) I Master DDC-bus interface I Deals with multiple levels of HDCP receivers and repeaters I Internal SHA-1 calculation I Controllable via I2C-bus I Low power dissipation I 1.8 V and 3.3 V power supplies I Power-down mode I Hard reset I Pin-to-pin compatible with TDA9983A/B and TDA9981A/B I Software compatible with TDA9983A/B and TDA9981A/B
3. Applications
I I I I I I I I I I Set-top box DVD player DVD recorder AV receiver Home theater Digital video camera Digital still camera Personal video recorder Media center PCs, graphic cards Switches
TDA9984A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
2 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
4. Quick reference data
Table 1. Quick reference data VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = -5 C to +85 C; unless otherwise specified. Typical values are measured at Tamb = 25 C and fclk = 150 MHz. Symbol VPP VDDA(FRO)(3V3) VDDA(PLL)(3V3) VDDD(3V3) VDDH(3V3) VDDC(1V8) VDDA(PLL)(1V8) Pcons Parameter programming voltage free running oscillator analog supply voltage (3.3 V) PLL analog supply voltage (3.3 V) digital supply voltage (3.3 V) HDMI supply voltage (3.3 V) core supply voltage (1.8 V) PLL analog supply voltage (1.8 V) power consumption input 480p, output 1080p input 1080i, output 1080p input 1080p, output 1080p Ptot total power dissipation TMDS output current added input 480p, output 1080p input 1080i, output 1080p input 1080p, output 1080p Ppd
[1] [2]
[1][3] [1][2] [1][4] [1][3] [1][2] [1][4]
Conditions
Min 5.0 3.0 3.0 3.0 3.0 1.65 1.65 -
Typ 5.25 3.3 3.3 3.3 3.3 1.8 1.8 500 742 320 630 872 450 30
Max 5.5 3.6 3.6 3.6 3.6 1.95 1.95 630 940 400 770 1080 540 40
Unit V V V V V V V mW mW mW mW mW mW mW
power dissipation in power-down mode
The maximum current consumption is in this configuration for this group of pins. Video format: a) Input 1080i, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. Video format: a) Input 480p, ITU656 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. Video format: a) Input 1080p, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF.
[3]
[4]
5. Ordering information
Table 2. Ordering information Package[1] Name TDA9984AHW HTQFP80
[1]
Type number
Description plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad
Version SOT841-4
A lead-free package is required to comply with the new legislation.
TDA9984A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
3 of 40
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Product data sheet Rev. 04 -- 15 January 2009
(c) NXP B.V. 2009. All rights reserved. TDA9984A_4
6. Block diagram
NXP Semiconductors
VDDA(PLL)(1V8) VPP 21 4 to 11 3 VDDD(3V3) VDDC(1V8) 59, 74 VDDH(3V3) 28, 34 VDDA(FRO)(3V3) 23 VDDA(PLL)(3V3) 16, 45 38 RST_N 42 HARD RESET A1 A0 40 41 I2C_SCL I2C_SDA 43 44 DDC_SDA DDC_SCL 19 20
13, 48, 71
TM AP0 to AP7
AUDIO FIFO AUDIO PROCESSING
AUDIO CONTENT
I2C-BUS SLAVE
DDC BUS MASTER
INTERRUPT GENERATION
17
INT
AUDIO INFO-FRAME CTS/N DATA ISLAND PACKET INSERTION I2C-BUS REGISTERS HPD MANAGEMENT 18 HPD
ACLK
12
ACR
VIDEO INFO-FRAME OTP MEMORY KEYS VHREF GENERATOR HDCP PROCESSING DOWNSAMPLER 4:4:4 to 4:2:2
RxSENSE 27 26 30 29 TMDS SERIALIZER
OTHER INFO-FRAME 66 CLOCK MANAGMENT
TXC+ TXC- TX0+
VCLK
HDMI 1.3 transmitter with 1080p upscaler embedded
TX0- TX1+ TX1- TX2+ TX2-
VPA[7:0]
68 to 70 75 to 79 57, 58 61 to 65, 67 49 to 56 2 1 80
3 x 8-bit RGB or YCbCr 4 : 4 : 4 2 x 12-bit YCbCr 4 : 2 : 2 semi-planar 1 x 12-bit YCbCr 4 : 2 : 2 ITU656 2 x 12-bit YCbCr 4 : 2 : 2 semi-planar 1 x 12-bit YCbCr 4 : 2 : 2 ITU656 UPSAMPLER 4:2:2 to 4:4:4
33 32 36 35
VPB[7:0] VPC[7:0] VSYNC/VREF HSYNC/HREF DE/FREF
VIDEO INPUT PROCESSOR
COLOR SPACE CONVERTER RGB to YCbCr YCbCr to RGB
24
EXT_SWING
UPSCALER 4:2:2 14, 47, 72 VSSD
TDA9984AHW
60, 73 VSSC
25, 31, 37 VSSH
22 VSSA(FRO)(3V3)
39 VSSA(PLL)(3V3)
46, 15 VSSA(PLL)(1V8)
001aag595
TDA9984A
The device can handle HDCP based on 1.2 features.
4 of 40
Fig 1.
Block diagram
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
7. Pinning information
74 VDDC(1V8) 71 VDDD(3V3) 80 DE/FREF
79 VPA[0]
78 VPA[1]
77 VPA[2]
76 VPA[3]
75 VPA[4]
70 VPA[5]
69 VPA[6]
68 VPA[7]
67 VPB[0]
65 VPB[1]
64 VPB[2]
63 VPB[3]
62 VPB[4]
HSYNC/HREF VSYNC/VREF VPP AP7 AP6 AP5 AP4 AP3 AP2
1 2 3 4 5 6 7 8 9
66 VCLK
73 VSSC
72 VSSD
61 VPB[5] 60 VSSC 59 VDDC(1V8) 58 VPB[6] 57 VPB[7] 56 VPC[0] 55 VPC[1] 54 VPC[2] 53 VPC[3] 52 VPC[4] 51 VPC[5] 50 VPC[6] 49 VPC[7] 48 VDDD(3V3) 47 VSSD 46 VSSA(PLL)(1V8) 45 VDDA(PLL)(1V8) 44 I2C_SDA 43 I2C_SCL 42 RST_N 41 A0 A1 40
001aag597
AP1 10 AP0 11 ACLK 12 VDDD(3V3) 13 VSSD 14 VSSA(PLL)(1V8) 15 VDDA(PLL)(1V8) 16 INT 17 HPD 18 DDC_SDA 19 DDC_SCL 20 TM 21 VSSA(FRO)(3V3) 22 VDDA(FRO)(3V3) 23 EXT_SWING 24 VSSH 25 TXC- 26 TXC+ 27
TDA9984AHW
VDDH(3V3) 28
TX0- 29
TX0+ 30
VSSH 31
TX1- 32
TX1+ 33
VDDH(3V3) 34
TX2- 35
TX2+ 36
VSSH 37
VDDA(PLL)(3V3) 38
Fig 2.
Pin configuration
7.1 Pin description
Table 3. Symbol HSYNC/HREF VSYNC/VREF VPP AP7 AP6 AP5 AP4 AP3
TDA9984A_4
Pin description Pin 1 2 3 4 5 6 7 8 Type[1] I I P I I I I I Description horizontal synchronization or reference input vertical synchronization or reference input programming voltage for OTP memory; connect to ground for digital core in normal operation audio port 7 input audio port 6 input audio port 5 input audio port 4 input audio port 3 input
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
VSSA(PLL)(3V3) 39
5 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
Pin description ...continued Pin 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Type[1] I I I I P G G P O I I/O I I G P I G O O P O O G O O P O O G P G I I I I I/O P G G Description audio port 2 input audio port 1 input audio port 0 input audio clock input digital supply voltage for I/O ports (3.3 V) digital ground for I/O ports analog ground for PLL PLL analog supply voltage (1.8 V) interrupt output; warns the external microprocessor that a special event has occurred hot plug detect input; 5 V tolerant DDC-bus data input/output; 5 V tolerant DDC-bus clock input; 5 V tolerant internal test mode input; connect to ground analog ground for free running oscillator analog supply voltage for free running oscillator (3.3 V) swing adjust input for TMDS output; a fixed resistor must be connected to VDDH(3V3) ground for TMDS (HDMI) transmitter negative clock channel for TMDS output positive clock channel for TMDS output supply voltage for TMDS (HDMI) transmitter (3.3 V) negative data channel 0 for TMDS output positive data channel 0 for TMDS output ground for TMDS (HDMI) transmitter negative data channel 1 for TMDS output positive data channel 1 for TMDS output supply voltage for TMDS (HDMI) transmitter (3.3 V) negative data channel 2 for TMDS output positive data channel 2 for TMDS output ground for TMDS (HDMI) transmitter analog supply voltage for PLL (3.3 V) analog ground for PLL I2C-bus slave address bit 1 input I2C-bus slave address bit 0 input hard reset input; active LOW I2C-bus clock input I2C-bus data input/output PLL analog supply voltage (1.8 V) analog ground for PLL digital ground for I/O ports
(c) NXP B.V. 2009. All rights reserved.
Table 3. Symbol AP2 AP1 AP0 ACLK VDDD(3V3) VSSD
VSSA(PLL)(1V8) VDDA(PLL)(1V8) INT HPD DDC_SDA DDC_SCL TM VSSA(FRO)(3V3) VDDA(FRO)(3V3) EXT_SWING VSSH TXC- TXC+ VDDH(3V3) TX0- TX0+ VSSH TX1- TX1+ VDDH(3V3) TX2- TX2+ VSSH VDDA(PLL)(3V3) VSSA(PLL)(3V3) A1 A0 RST_N I2C_SCL I2C_SDA VDDA(PLL)(1V8) VSSA(PLL)(1V8) VSSD
TDA9984A_4
Product data sheet
Rev. 04 -- 15 January 2009
6 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
Pin description ...continued Pin 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Type[1] P I I I I I I I I I I P G I I I I I I I I I I P G G P I I I I I I Description digital supply voltage for I/O ports (3.3 V) video port C input bit 7 (MSB) video port C input bit 6 video port C input bit 5 video port C input bit 4 video port C input bit 3 video port C input bit 2 video port C input bit 1 video port C input bit 0 (LSB) video port B input bit 7 (MSB) video port B input bit 6 supply voltage for digital core (1.8 V) ground for digital core video port B input bit 5 video port B input bit 4 video port B input bit 3 video port B input bit 2 video port B input bit 1 video pixel clock input video port B input bit 0 (LSB) video port A input bit 7 (MSB) video port A input bit 6 video port A input bit 5 digital supply voltage for I/O ports (3.3 V) digital ground for I/O ports ground for digital core supply voltage for digital core (1.8 V) video port A input bit 4 video port A input bit 3 video port A input bit 2 video port A input bit 1 video port A input bit 0 video data enable or field reference input
Table 3. Symbol VDDD(3V3) VPC[7] VPC[6] VPC[5] VPC[4] VPC[3] VPC[2] VPC[1] VPC[0] VPB[7] VPB[6] VDDC(1V8) VSSC VPB[5] VPB[4] VPB[3] VPB[2] VPB[1] VCLK VPB[0] VPA[7] VPA[6] VPA[5] VDDD(3V3) VSSD VSSC VDDC(1V8) VPA[4] VPA[3] VPA[2] VPA[1] VPA[0] DE/FREF
[1]
P = Power supply; G = Ground; I = Input; O = Output.
TDA9984A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
7 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8. Functional description
The TDA9984A is designed to convert digital data (video and audio) provided by a Set-Top Box or DVD into an HDMI output, which could be used in TV with HDMI or DVI input. The TDA9984A is able to output HDMI with the formats:
* RGB * YCbCr 4 : 4 : 4 * YCbCr 4 : 2 : 2
The video data input formats are:
* * * *
RGB YCbCr 4 : 4 : 4 YCbCr 4 : 2 : 2 semi-planar YCbCr 4 : 2 : 2 ITU656-like
It can also handle audio formats:
* 4 x I2S-bus channels * One S/PDIF channel * Dolby-True HD and DTS-HD through the use of HBR interface 8.1 Video processing
The TDA9984A has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0] and can handle any of the following video input modes:
* * * *
RGB with 8-bit for each component YCbCr 4 : 4 : 4 with 8-bit for each component YCbCr 4 : 2 : 2 semi-planar with up to 12-bit for each component (Y, Cb and Cr) YCbCr 4 : 2 : 2 ITU656 with up to 12-bit data depth
The TDA9984A can be set to latch data at either the rising or the falling edge.
8.1.1 Internal assignment
The aim of the video input processor is to map internally the incoming data to the corresponding mode, which can be handled by the video processing. The device expects to have a big endian digital stream at its input. The internal signal name VP[23:0] is assigned depending on the input mode as defined in Figure 3.
VPA[7:0] VPB[7:0] VPC[7:0] VIDEO INPUT PROCESSOR VP[23:0]
001aag599
Fig 3.
TDA9984A_4
Internal assignment of VP[23:0]
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
8 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
The device can swap and invert (in case of a little endian stream) the incoming video data via the I2C-bus registers VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 (page 00h) to match the expectation of the video processing block; see Table 4. When input ports are not used, it is possible to map them to internal ground via the I2C-bus registers ENA_VP_0, ENA_VP_1, ENA_VP_2, GND_VP_0, GND_VP_1 and GND_VP_2 (page 00h).
Table 4. Internal assignment RGB G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0] YCbCr 4:4:4 VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] VP[16] VP[15] VP[14] VP[13] VP[12] VP[11] VP[10] VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] VP[1] VP[0] Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] Cb[7] Cb[6] Cb[5] Cb[4] Cb[3] Cb[2] Cb[1] Cb[0] Cr[7] Cr[6] Cr[5] Cr[4] Cr[3] Cr[2] Cr[7] Cr[0] 4 : 2 : 2 semi-planar Y[11] Y[10] Y[9] Y[8] Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0] CbCr[11] CbCr[10] CbCr[9] CbCr[8] CbCr[7] CbCr[6] CbCr[5] CbCr[4] CbCr[3] CbCr[2] CbCr[1] CbCr[0] 4 : 2 : 2 ITU656-like YCbCr[11] YCbCr[10] YCbCr[9] YCbCr[8] YCbCr[7] YCbCr[6] YCbCr[5] YCbCr[4] YCbCr[3] YCbCr[2 YCbCr[1] YCbCr[0] -
Internal port
8.1.2 Input format mappings
See Table 5 for more information concerning input format supported.
TDA9984A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
9 of 40
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Product data sheet Rev. 04 -- 15 January 2009 [1]
(c) NXP B.V. 2009. All rights reserved. TDA9984A_4
NXP Semiconductors
Table 5.
Inputs of video input formatter Channels 3 x 8-bit Sync external embedded Rising edge X X X X X X embedded X X X X X embedded X X X up to 2 x 12-bit semi-planar external embedded X X X X Falling edge Double edge[1] Transmission Pixel clock input format (MHz) ITU656-like ITU656-like ITU656-like ITU656-like ITU656-like ITU656-like SMPTE293M SMPTE293M SMPTE293M SMPTE293M 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 150 MHz 54.054 MHz 54.054 MHz 27.027 MHz 54.054 MHz 54.054 MHz 27.027 MHz 148.5 MHz 148.5 MHz 148.5 MHz 148.5 MHz Maximum input format 480p/576p 480p/576p 480p/576p 480p/576p 480p/576p 480p/576p 1080p 1080p 1080p 1080p Section 8.1.2.8 Section 8.1.2.6 Section 8.1.2.4 Section 8.1.2.5 Section 8.1.2.3 Section 8.1.2.2 Reference Section 8.1.2.1
Space color Format RGB 4:4:4
YCbCr
4:4:4
3 x 8-bit
external
YCbCr
4:2:2
up to 1 x 12-bit semi-planar
external
HDMI 1.3 transmitter with 1080p upscaler embedded
Section 8.1.2.7
Double edge means both rising and falling edges.
TDA9984A
10 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.1
RGB 4 : 4 : 4 external sync input (rising edge)
Table 6. RGB 4 : 4 : 4 mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] RGB 4 : 4 : 4 B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] RGB 4 : 4 : 4 G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] RGB 4 : 4 : 4 R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF RGB 4 : 4 : 4 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] B0[7:0] B1[7:0] B2[7:0] B3[7:0] ... Bxxx[7:0] Bxxx[7:0]
VPB[7:0]
G0[7:0]
G1[7:0]
G2[7:0]
G3[7:0]
...
Gxxx[7:0]
Gxxx[7:0]
VPC[7:0]
R0[7:0]
R1[7:0]
R2[7:0]
R3[7:0]
...
Rxxx[7:0]
Rxxx[7:0]
001aag380
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 4.
Pixel encoding RGB 4 : 4 : 4 external sync input (rising edge)
TDA9984A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
11 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.2
YCbCr 4 : 4 : 4 external sync input (rising edge)
Table 7. YCbCr 4 : 4 : 4 mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 4 : 4 Cb[0] Cb[1] Cb[2] Cb[3] Cb[4] Cb[5] Cb[6] Cb[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 4 : 4 Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 4 : 4 Cr[0] Cr[1] Cr[2] Cr[3] Cr[4] Cr[5] Cr[6] Cr[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 4 : 4 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] Cb0[7:0] Cb1[7:0] Cb2[7:0] Cb3[7:0] ... Cbxxx[7:0] Cbxxx[7:0]
VPB[7:0]
Y0[7:0]
Y1[7:0]
Y2[7:0]
Y3[7:0]
...
Yxxx[7:0]
Yxxx[7:0]
VPC[7:0]
Cr0[7:0]
Cr1[7:0]
Cr2[7:0]
Cr3[7:0]
...
Crxxx[7:0]
Crxxx[7:0]
001aag381
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 5.
Pixel encoding YCbCr 4 : 4 : 4 external sync input (rising edge)
TDA9984A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
12 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.3
YCbCr 4 : 2 : 2 ITU656-like external sync input (rising edge)
Table 8. YCbCr 4 : 2 : 2 ITU656-like rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 2 : 2 (ITU656-like) Cb[0] Y0[0] Cb[1] Y0[1] Cb[2] Y0[2] Cb[3] Y0[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[0] Y1[1] Y1[2] Y1[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 (ITU656-like) Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Control Pin YCbCr 4 : 2 : 2 HSYNC/HREF used VSYNC/VREF used DE/FREF used
Cb[10] Y0[10] Cr[10] Y1[10] Cb[11] Y0[11] Cr[11] Y1[11]
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Cb0[11:0] Y0[11:0] Cr0[11:0] Y1[11:0] ... Crxxx[11:0] Yxxx[11:0]
001aag383
VPB[7:0]; VPA[3:0]
Fig 6.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external sync input (rising edge)
TDA9984A_4
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.4
YCbCr 4 : 2 : 2 ITU656-like external sync input (rising and falling)
Table 9. YCbCr 4 : 2 : 2 ITU656-like double edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] Cb[0] Y0[0] Cb[1] Y0[1] Cb[2] Y0[2] Cb[3] Y0[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[0] Y1[1] Y1[2] Y1[3] Video port B YCbCr 4 : 2 : 2 (ITU656-like) Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Cb[10] Cb[11] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 used used used YCbCr 4 : 2 : 2 (ITU656-like) Pin
Y0[10] Cr[10] Y0[11] Cr[11]
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Cb0[11:0] Y0[11:0] Cr0[11:0] Y1[11:0] ... Crxxx[11:0] Yxxx[11:0]
001aag382
VPB[7:0]; VPA[3:0]
Fig 7.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external sync input (rising and falling)
TDA9984A_4
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.5
YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising edge)
Table 10. YCbCr 4 : 2 : 2 ITU656-like embedded rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] Cb[0] Y0[0] Cb[1] Y0[1] Cb[2] Y0[2] Cb[3] Y0[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[0] Y1[1] Y1[2] Y1[3] Video port B YCbCr 4 : 2 : 2 (ITU656-like) Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 not used not used not used YCbCr 4 : 2 : 2 (ITU656-like) Pin
Cb[10] Y0[10] Cb[11] Y0[11]
VCLK
VPB[7:0]; VPA[3:0]
Cb0[11:0]
Y0[11:0]
Cr0[11:0]
Y1[11:0]
...
Crxxx[11:0]
Yxxx[11:0]
001aag385
Fig 8.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising edge)
TDA9984A_4
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.6
YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising and falling)
Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded double edge mappings Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] Cb[0] Cb[1] Cb[2] Cb[3] Y0[0] Y0[1] Y0[2] Y0[3] Cr[0] Cr[1] Cr[2] Cr[3] Y1[0] Y1[1] Y1[2] Y1[3] Video port B YCbCr 4 : 2 : 2 (ITU656-like) Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] Control Pin YCbCr 4 : 2 : 2 HSYNC/HREF not used VSYNC/VREF not used DE/FREF not used YCbCr 4 : 2 : 2 (ITU656-like) Pin
Cb[10] Y0[10] Cb[11] Y0[11]
VCLK
VPB[7:0]; VPA[3:0]
Cb0[11:0]
Y0[11:0]
Cr0[11:0]
Y1[11:0]
...
Crxxx[11:0]
Yxxx[11:0]
001aag384
Fig 9.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising and falling)
TDA9984A_4
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.7
YCbCr 4 : 2 : 2 semi-planar external input (rising edge)
Table 12. YCbCr 4 : 2 : 2 semi-planar rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 2 : 2 semi-planar Y0[0] Y0[1] Y0[2] Y0[3] Cb[0] Cb[1] Cb[2] Cb[3] Y1[0] Y1[1] Y1[2] Y1[3] Cr[0] Cr[1] Cr[2] Cr[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 semi-planar Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 2 : 2 semi-planar Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Cb[10] Cb[11] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Control Pin YCbCr 4:2:2
HSYNC/HREF used VSYNC/VREF used DE/FREF used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Y0[11:0] Y1[11:0] Y2[11:0] Y3[11:0] Y4[11:0] Y5[11:0] ...
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
Cb0[11:0]
Cr0[11:0]
Cb2[11:0]
Cr2[11:0]
Cb4[11:0]
Cr4[11:0]
...
001aag386
Fig 10. Pixel encoding YCbCr 4 : 2 : 2 semi-planar external input (rising edge)
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.8
YCbCr 4 : 2 : 2 semi-planar embedded sync input (rising edge)
Table 13. YCbCr 4 : 2 : 2 semi-planar embedded rising edge mapping Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 2 : 2 semi-planar Y0[0] Y0[1] Y0[2] Y0[3] Cb[0] Cb[1] Cb[2] Cb[3] Y1[0] Y1[1] Y1[2] Y1[3] Cr[0] Cr[1] Cr[2] Cr[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 semi-planar Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 2 : 2 semi-planar Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Cb[10] Cb[11] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Control Pin YCbCr 4:2:2
HSYNC/HREF not used VSYNC/VREF not used DE/FREF not used
VCLK
VPB[7:0]; VPA[3:0]
Y0[11:0]
Y1[11:0]
Y2[11:0]
Y3[11:0]
Y4[11:0]
Y5[11:0]
...
VPC[7:0]; VPA[7:4]
Cb0[11:0]
Cr0[11:0]
Cb2[11:0]
Cr2[11:0]
Cb4[11:0]
Cr4[11:0]
...
001aag387
Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded sync input (rising edge)
TDA9984A_4
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.3 Synchronization
The TDA9984A can be synchronized with external input signals HSYNC and VSYNC or with extraction of the sync information from embedded sync codes (SAV/EAV) inside the video. 8.1.3.1 Timing extraction generator This block can extract the synchronization signals HREF, VREF and FREF from SAV and EAV in case of embedded synchronization in the data stream. Synchronization signals can be embedded in YCbCr 4 : 2 : 2 ITU656 (up to 1 x 12-bit) and semi-planar (up to 2 x 12-bit). 8.1.3.2 Data enable generator TDA9984A contains a Data Enable (DE) generator. This circuit generates an internal DE signal for a system which does not provide one. The DE generator is controlled via the I2C-bus register.
8.1.4 Input and output video format
Due to the flexible video input formatter, the TDA9984A can accept a large range of inputs formats. This flexibility allows the TDA9984A to be compatible with the maximum number of MPEG decoders. Moreover, these input formats may be changed in many ways (space color converter, upsampler and scaler) to be transmitted across the HDMI link. Table 14 gives the possible inputs and outputs.
Table 14. Input Space color Format RGB 4:4:4 Channels 3 x 8-bit no scaling Inputs and outputs capability Scaler Output Space color RGB YCbCr YCbCr YCbCr 4:4:4 3 x 8-bit no scaling RGB YCbCr YCbCr YCbCr 4:2:2 up to 1 x 12-bit semi-planar scaling RGB YCbCr YCbCr up to 2 x 12-bit semi-planar scaling RGB YCbCr YCbCr Format 4:4:4 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 Channels 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit
8.1.5 Scaler unit
8.1.5.1 Scaler features The scaler unit has the following features:
* Up-scaling only: to expand input image horizontally and vertically * Deinterlacer embedded (no need of output memory) * Data processing: 12-bit data width
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HDMI 1.3 transmitter with 1080p upscaler embedded
* Maximum output operating frequency is 148.5 MHz; HDTV supported 1080p both PAL
and NTSC
* Input video standards YCbCr 4 : 2 : 2 semi-planar and ITU656 (no RGB, nor
YCbCr 4 : 4 : 4) 8.1.5.2 Input and output video scaler The scaler will convert the standard definition (high definition respectively) video signals (480i/576i, 480p/576p and 720p, 1080i respectively) into 1080p as described in Figure 12. Remark: All 4 : 2 : 2 input video formats can be bypassed, as well as all RGB and YCbCr 4 : 4 : 4 input data, which will be directly fed to the color space converter.
VIDEO STANDARD OUTPUT 21, 22 (PAL) x 720 576i 6, 7 (NTSC)
FORMAT 861B
17, 18
2, 3
16
19
20
x 1080p
1280
1920
1920
1280
1920
FORMAT 861B 2, 3 VIDEO STANDARD INPUT 4 5 6, 7 (NTSC) 16 17, 18 19 20 21, 22 (PAL) 31 720 1280 1920 720 1920 720 1280 1920 720 1920 x 480p x 720p x 1080i x 480i x 1080p x 576p x 720p x 1080i x 576i x 1080p
(1) (2) (3) (1) (1)
(2) (2) (4)
(4) (5) (6) (1) (5) (1) (1) (2) (3) (1) (1) (2) (2) (4)
(4) (5) (6) (1) (5) (1)
001aag603
All upscaling modes are available only for YCbCr 4 : 2 : 2 input format. (1) Pass-through (2) Upscaling (3) Upscaling and interlacing (4) Deinterlacing (5) Deinterlacing and upscaling (6) Deinterlacing, upscaling and interlacing
Fig 12. Input and output video scaler
8.1.6 Upsampler
The incoming YCbCr 4 : 2 : 2 (2 x 12-bit) data stream format can be upsampled into an 8-bit YCbCr 4 : 4 : 4 (3 x 8-bit) data stream by repeating or linearly interpolating the chrominance pixels.
TDA9984A_4
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Product data sheet
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1920
720
720
720
x 1080p
x 1080i
x 1080i
x 480p
x 720p
x 576p
x 720p
x
480i
31
4
5
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.7 Color space converter
The color-space converter is used to convert input video data from one type to another color space (e.g. RGB to YCbCr and YCbCr to RGB). This block can be bypassed and each coefficient is programmable by the I2C-bus registers. C 11 C 12 C 13 GY Oin GY YG CrR = C 21 C 22 C 23 x RCr + Oin RCr CbB C 31 C 32 C 33 BCb Oin BCb Oout YG + Oout CrR Oout CbB
(1)
8.1.8 Downsampler
This block works only with YCbCr input format. These filters downsample the Cb and Cr signals by a factor of two. A delay is added on the G/Y channel, which corresponds to the pipeline delay of the filters, to put the Y channel in phase with the Cb and Cr channel.
8.2 Audio processing
The TDA9984A is compatible with audio features as per HDMI specification, Rev. 1.3:
* S/PDIF * I2S-bus up to four channels * Dolby-True HD and DTS-HD through the use of HBR interface
S/PDIF, I2S-bus or HBR can be selected via the I2C-bus. Only one audio format can be used at a same time. Table 15 shows the audio port allocation.
Table 15. Audio port AP0 AP1 AP2 AP3 AP4 AP5 AP6 AP7 ACLK Audio port configuration Format S/PDIF MCLK S/PDIF input AUX (internal test) I2S-bus WS (word select) I2S-bus channel 0 I2S-bus I2S-bus AUX (internal test) SCK channel 1 channel 2 HBR WS (word select) HBR channel 0 HBR channel 1 HBR channel 2 HBR channel 3 AUX (internal test) SCK
I2S-bus channel 3
All audio ports are LV-TTL compatible. It is possible to map internally an unused port to internal ground via the I2C-bus registers ENA_APx and GND_APx on page 00h (both audio inputs and clock input as well).
8.2.1 S/PDIF
The audio port AP6 is used for this feature. In this format, the TDA9984A supports 2-channel uncompressed PCM data (IEC 60958) layout 0, or compressed bit stream up to 8 multi-channels (Dolby Digital, DTS, AC3, etc.) layout 1.
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HDMI 1.3 transmitter with 1080p upscaler embedded
The TDA9984A is able to recover the original clock from the S/PDIF signal (no need of external clock). In addition, it can also use an external clock to decode the S/PDIF signal.
8.2.2 I2S-bus
There are 4 x I2S-bus stereo inputs channels (AP1, AP2, AP3 and AP4) which allow carrying eight uncompressed audio channels. The I2S-bus input interface receives an I2S-bus signal including serial data in, word select and serial clock. Various I2S-bus formats are supported and can be selected by setting the appropriate bits of the register. Typical waveforms for the I2S-bus signals at 64fs are given in Figure 13.
DATA
LEFT CHANNEL (n-1)
RIGHT CHANNEL (n-1)
LEFT CHANNEL (n)
RIGHT CHANNEL (n)
LEFT CHANNEL (n+1)
RIGHT CHANNEL (n+1)
WS
MSB
24-bit audio sample word
LSB 0 0
0
ACLK(64fs)
001aag607
a. Philips format
LEFT CHANNEL (n-1) RIGHT CHANNEL (n-1) LEFT CHANNEL (n) RIGHT CHANNEL (n) LEFT CHANNEL (n+1) RIGHT CHANNEL (n+1)
DATA
WS
MSB
24-bit audio sample word
LSB 0 0
0
ACLK(64fs)
001aag608
b. Left justified format
LEFT CHANNEL (n-1) RIGHT CHANNEL (n-1) LEFT CHANNEL (n) RIGHT CHANNEL (n) LEFT CHANNEL (n+1) RIGHT CHANNEL (n+1)
DATA
WS
00
0
MSB
24-bit audio sample word
LSB
ACLK(64fs)
001aag609
c. Right justified format Fig 13. I2S-bus formats
The I2S-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency fs. Audio samples with a precision better than 24 bits are truncated to 24-bit format.
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HDMI 1.3 transmitter with 1080p upscaler embedded
If the input clock has a frequency of 32fs, only 16-bit audio samples can be received. If the input clock has a frequency of 64fs and is left justified or Philips, the audio word is truncated to 24-bit format and padded with zeros. If the input clock has a frequency of 64fs and is right justified, audio sample must be strictly 24-bit length. The word select signal WS indicates whether left or right channel information is transferred over the serial data.
8.2.3 High bit rate audio
The High Bit Rate audio format is used to support both DTS-HD and Dolby-True HD audio format provided for instance by Blu-Ray DVD. The transmitter is capable to receive a single High Bit Rate IEC 61937 stream at a frame rate of 768 kHz. This is typically stripped across 4 x I2S-bus interface to the HDMI transmitter with a corresponding I2S-bus clock rate of 192 kHz. As for I2S-bus, no additional information is required on the audio infoframe. All relevant information are carried on the stream through the use of the channel status bit via the I2C-bus table.
8.3 HDCP processing
8.3.1 High-bandwidth digital content protection
The HDMI transmitter contains an HDCP function, which encrypts the transmitted stream content (both video and audio). This function can be enabled and disabled via the I2C-bus. The keys can be stored internally in OTP non-volatile memory or can be loaded via the I2C-bus. As the keys are stored internally, the security is maximized. 8.3.1.1 Repeater function The TDA9984A can be used in a repeater device according to the HDCP specification, Rev 1.2. The TDA9984A is able to store the KSV list of a maximum of 127 devices in a register memory. 8.3.1.2 SHA-1 To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the downstream repeater. For security purposes and in order to relieve the microcontroller, the SHA-1 has been implemented within the TDA9984A. This calculation is worked out after the transmitter has loaded the KSV list (see HDCP specification, Rev 1.2). If SHA-1 calculated by transmitter equals the SHA-1 calculated by repeater, then an interrupt is sent.
8.4 TMDS serializer
8.4.1 RxSense detection
The TDA9984A has the capability to sense the receiver connectivity and working behavior. This feature detects the presence of the 50 pull-up resistor RT on the downstream side onto the TMDS clock channel.
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HDMI 1.3 transmitter with 1080p upscaler embedded
VDDA
RT RT
TRANSMITTER Z0 D D RECEIVER
001aag601
Fig 14. Receiver sensitivity detection
As long as the receiver is connected to the transmitter and powered up, bit RXS_FIL is set to logic 1 (see register INT_FLAGS_3, page 00h, address 12h). As soon as the cable is unplugged or the receiver side is powered off (assuming in this case that VDD is switched off), the RxSense generates an interrupt inside the TDA9984A, changing the value of bit RXS_FIL to logic 0. This allows the application to stop sending unnecessary video content. This feature is very useful when the receiver has been recovered from an off-state and does not generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case, RxSense will generate an interrupt so that the TDA9984A restarts sending video. Remark: According to the HDMI specification, only the HPD interrupt allows the application to read the EDID. RxSense is not mandatory to initialize the EDID reading procedure.
8.4.2 TMDS output buffers
The TMDS output amplitude can be adjusted via an external resistor connected between pins EXT_SWING and VDDH(3V3); see Figure 15. It is strongly recommended to use REXT_SWING = 610 1 % to get a nominal swing of 500 mV. By doing so, the TDA9984A shall meet the minimum low-level output voltage as per HDMI specification, Rev 1.3a table 4-15.
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TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
650
(1)
001aag602
Vo(se) (mV) 550
(2)
450
(3)
350 500
600
700 REXT_SWING ()
800
(1) Swing character data (2) Upper limit (600 mV) (3) Lower limit (400 mV)
Fig 15. TMDS single-ended output swing as a function of external resistor REXT_SWING
8.4.3 Pixel repetition
To transmit video formats with pixel rates below 25 mega samples per second or to increase the number of audio sample packets in each frame, the TDA9984A uses pixel repetition to increase the number of pixels sent by the frame. The pixel clock is multiplied by the same factor as given in Table 16.
Table 16. PR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Others Pixel repetition Pixel repetition factor no repetition: pixel sent once 2 times: pixel repeated once 3 times 4 times 5 times 6 times 7 times 8 times 9 times 10 times reserved
8.5 Control blocks
8.5.1 Clock management
The system clock is composed of a series of three PLLs, which will generates different clocks in the system taking into account the double edge, the scaling ratio and the serialization.
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Here is described briefly the clock system architecture:
* PLL double edge: generates a clock at twice the VCLK input frequency to capture
correctly the data at the video formatter input
* PLL scaling: creates a new video processing scaled clock taking into account the
scaling ratio programmed in the scaler
* PLL serializer: a system clock generator, which enables the stream produced by the
encoder to be transmitted on the TMDS data channel at ten times or above the sampling rate; see Section 8.4.3 Each PLL can be bypassed via the I2C-bus and then external clock VCLK can be provided independently to each block.
8.5.2 Interrupt controller
Pin INT is used to alert the microcontroller that a critical event concerning the HDMI has occurred. Some of theses interrupts are maskable. See Table 17 for the interrupt types generated by the TDA9984A.
Table 17. Interrupt Domain HDCP Interrupt name r0 pj sha-1 bstatus bcaps t0 security HPD RxSense EDID Interrupt hpd rx_sense edid_block_rd sw_intsoftware r0 = R'0 check done pj = P'j check fails V = V' check success bstatus available bcaps available HDCP goes to initial state HDCP encryption is off or blue screen removed transition on HPD input transition on RxSense EDID block read finished test purpose not maskable maskable Interrupts Definition Maskable feature maskable
8.5.3 Hot plug detection
Pin HPD is the hot plug detect pin; it is 5 V input tolerant. When asserted, the hot plug detect signal tells the transmitter that the receiver is connected. When changing from LOW to HIGH, the TDA9984A has to read EDID to match the video format to the format the receiver can handle.
8.5.4 Initialization
After power-up, the TDA9984A is activated by a hard reset. Pin RST_N can be used to activate the TDA9984A in a known state. The device also offers the possibility to perform a soft reset that will affect a certain number of I2C-bus registers, but not all of them. This soft reset is also mandatory for a proper initialization of the device.
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8.5.5 Power management
The TDA9984A can be powered down via the I2C-bus register. In this mode, all PLLs are switched off and the biasing structure of the output stage is disconnected (all activity is reduced). Therefore, the TDA9984A has a very low power consumption which is suitable for portable applications.
8.6 DDC-bus interface
8.6.1 DDC-bus channel
The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at Standard-mode (100 kHz) and Fast-mode (400 kHz). The DDC-bus is used as a master interface in case of EDID reading, and while proceeding for HDCP. It is recommended not going beyond 100 kHz for EDID as claimed by the HDMI specification. This frequency is linked to the internal free running oscillator whose nominal frequency is 30 MHz as: f FRO f DDC = --------------------------------3 x 2N clk - div Where: fFRO = free running oscillator frequency Nclk-div = value set by register Then for convenience, it is recommended to keep the same frequency for HDCP purpose. (2)
8.6.2 E-EDID
8.6.2.1 E-EDID reading As a master interface for the EDID process, the DDC-bus is compliant to the I2C-bus specification and has the possibility of the repeat and start condition to enable quick access to the EDID content, as well as the large EDID reading possibility (with the use of a segment pointer). The TDA9984A has a full I2C-bus page (page 09h) dedicated to the EDID where one block can be stored. The block can be read by the microprocessor to determine the supported video and audio format of the downstream side. Remark: When the block is read by the TDA9984A, it generates an interrupt to warn the main processor that the TDA9984A is ready to transmit the content. Once the content is read-out by the microprocessor, it can allow reading other blocks if required. 8.6.2.2 HDMI and DVI receiver discrimination This information is located in the E-EDID receiver part, more exactly in the `Vendor Specific Data block within the first CEA EDID timing extension. If the 24-bit IEEE Registration Identifier contains the value 00 0C03h, then the receiver will support HDMI; otherwise the device shall be treated as a DVI device. However, even though the TDA9984A have directly access to that information, this is the task of the microcontroller to ask to switch from DVI to HDMI mode.
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8.7 I2C-bus interface
The I2C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant. Pin I2C_SCL is only an input pin. Both Fast-mode (400 kHz) and Standard-mode (100 kHz) are supported. The registers of the TDA9984A can be accessed via the I2C-bus. All registers are R/W except some, which cannot be read for confidentiality. The TDA9984A is used as a slave I2C-bus device. Bits A0 and A1 of the I2C-bus device address are externally selected by pins A0 and A1 (see Table 18).
Table 18. A6 1 Device address W/R A4 1 A3 0 A2 0 A1 pin A1 A0 pin A0 0/1 A5 1
Device address
The I2C-bus access format is shown in Figure 16. Firstly, the master writes the TDA9984A address and the subaddress to access the specific register, and then the data.
123456789123456789123456789 SCL SDA SLAVE ADDRESS SUBADDRESS DATA STOP
001aaf292
Fig 16. I2C-bus access
9. I2C-bus registers definitions
9.1 Memory page management
The I2C-bus memory is split into several pages and the selection between pages is made with common register CURPAGE_ADR. It is only necessary to write in this register once to change the current page. So multiple read or write operations in the same page need a write register CURPAGE_ADR once at the beginning.
Table 19. 00h 01h 02h 09h 10h 11h 12h Memory pages Memory page description general control scaler and PLL scaling PLL settings EDID control page InfoFrames and packets audio settings and content info packets HDCP and OTP
Page address
9.2 ID version
The ID-version readable via I2C-bus is defined as follows:
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HDMI 1.3 transmitter with 1080p upscaler embedded
* TDA9984AHW will have the value 1000 XXXX
The four LSBs are used for indicating the die version.
10. Limiting values
Table 20. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD(3V3) VDD(1V8) VDD Tstg Tamb Tj Vesd Parameter supply voltage (3.3 V) supply voltage (1.8 V) supply voltage difference storage temperature ambient temperature junction temperature electrostatic discharge voltage human body model Conditions Min -0.5 -0.5 -0.5 -55 -5 Max +4.6 +2.5 +0.5 +150 +85 +125 2000 Unit V V V C C C V
11. Thermal characteristics
Table 21. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 26.5 Unit K/W
12. Static characteristics
Table 22. Supplies VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = -5 C to +85 C; unless otherwise specified. Typical values are measured at Tamb = 25 C and fclk = 150 MHz. Symbol VPP VDDA(FRO)(3V3) VDDA(PLL)(3V3) VDDD(3V3) VDDH(3V3) VDDC(1V8) VDDA(PLL)(1V8) IDDA(FRO)(3V3) IDDA(PLL)(3V3) IDDD(3V3) IDDH(3V3) IDDA(PLL)(1V8) IDDC(1V8)
TDA9984A_4
Parameter programming voltage free running oscillator analog supply voltage (3.3 V) PLL analog supply voltage (3.3 V) digital supply voltage (3.3 V) HDMI supply voltage (3.3 V) core supply voltage (1.8 V) PLL analog supply voltage (1.8 V) free running oscillator analog supply current (3.3 V) PLL analog supply current (3.3 V) digital supply current (3.3 V) HDMI supply current (3.3 V) PLL analog supply current (1.8 V) core supply current (1.8 V)
Conditions
Min 5.0 3.0 3.0 3.0 3.0 1.65 1.65 -
Typ 5.25 3.3 3.3 3.3 3.3 1.8 1.8 0.1 6 14 75 283
Max 5.5 3.6 3.6 3.6 3.6 1.95 1.95 1 6.4 5 15 92 345
Unit V V V V V V V mA mA mA mA mA mA
input 1080i, output 1080p input 1080p, output 1080p input 1080i, output 1080p input 1080i, output 1080p
[1][2] [1][4]
-
[1][2] [1][2]
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Table 22. Supplies ...continued VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = -5 C to +85 C; unless otherwise specified. Typical values are measured at Tamb = 25 C and fclk = 150 MHz. Symbol Pcons Parameter power consumption Conditions input 480p, output 1080p input 1080i, output 1080p input 1080p, output 1080p Ptot total power dissipation TMDS output current added input 480p, output 1080p input 1080i, output 1080p input 1080p, output 1080p Ppd power dissipation in power-down mode
The maximum current consumption is in this configuration for this group of pins. Video format: a) Input 1080i, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. Video format: a) Input 480p, ITU656 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF. Video format: a) Input 1080p, YCbCr 4 : 2 : 2 embedded sync, 48 kHz S/PDIF 2 channels. b) Output 1080p, YCbCr 4 : 2 : 2, 48 kHz S/PDIF.
[1][3] [1][2] [1][4] [1][3] [1][2] [1][4]
Min -
Typ 500 742 320 630 872 450 30
Max 630 940 400 770 1080 540 40
Unit mW mW mW mW mW mW mW
[1] [2]
[3]
[4]
Table 23. LV-TTL digital inputs VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = -5 C to +85 C; typical values are measured at Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE and RST_N VIL VIH VIL VIH VOL VOH LOW-level input voltage HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage CL = 10 pF; IOL = 2 mA CL = 10 pF; IOH = -2 mA 2.0 2.0 2.4 0.8 0.8 0.4 V V V V V V
5 V tolerant input: pin HPD
Output: pin INT
Table 24. TMDS outputs VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = -5 C to +85 C; typical values are measured at Tamb = 25 C; unless otherwise specified. Symbol VO(dif) Parameter differential output voltage Conditions REXT_SWING = 610 (1 % tolerance); RL = 50 Min 480 Typ 525 Max 560 Unit mV TMDS output pins: TX0-, TX0+, TX1-, TX1+, TX2-, TX2+, TXC- and TXC+
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13. Dynamic characteristics
Table 25. Timing characteristics VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; VPP = 0 V; Tamb = -5 C to +85 C; typical values are measured at Tamb = 25 C; unless otherwise specified. Symbol fclk(max) clk tsu(D) th(D) Audio input S/PDIF mode fs fclk Tclk clk HBR mode fs fs fclk(max) fSCL I2C-bus; fSCL sampling frequency sampling frequency maximum clock frequency SCL clock frequency Standard-mode Fast-mode 5 V tolerant; slave bus: pins I2C_SDA and I2C_SCL SCL clock frequency Standard-mode Fast-mode
[1] In case of MCLK is required, this frequency has to be coherent with S/PDIF input.
Parameter maximum clock frequency clock duty cycle data input set-up time data input hold time
Conditions pin VCLK pin VCLK
Min 150 40 1.0 0.8
Typ 50 -
Max 60 -
Unit MHz % ns ns
Video inputs; see Figure 17
sampling frequency clock frequency clock period clock duty cycle
2 channels pin AP5 (MCLK) pin AP5 (MCLK)
[1] [1]
32 13.3 40 32 150 -
192 -
192 75 60 192 192 100 400 100 400
kHz MHz ns % kHz kHz MHz kHz kHz kHz kHz
I2S-bus mode TMDS output pins: TX0-, TX0+, TX1-, TX1+, TX2-, TX2+, TXC- and TXC+ DDC-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL
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HDMI 1.3 transmitter with 1080p upscaler embedded
VCLK VPA[7:0] VPB[7:0] VPC[7:0] DE, HSYNC, VSYNC
tsu(D)
th(D)
001aag604
a. Sync on rising edge
VCLK VPA[7:0] VPB[7:0] VPC[7:0] DE, HSYNC, VSYNC
tsu(D)
th(D)
001aag605
b. Sync on falling edge
VCLK VPA[7:0] VPB[7:0] VPC[7:0] DE, HSYNC, VSYNC tsu(D) th(D) tsu(D) th(D)
001aag606
c. Sync on rising and falling (double) edge
Data is not allowed to change in the shaded area.
Fig 17. Set-up and hold time for various clock modes
13.1 Input format
Mapping of the video ports:
* Port VPA has been mapped to Cb for YCbCr space and B for RGB color space * Port VPB has been mapped to Y for YCbCr space and G for RGB color space * Port VPC has been mapped to Cr for YCbCr space and R for RGB color space
Table 26. Input pins Video port A VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7]
TDA9984A_4
Input format Signal RGB 4:4:4 Cb[0]/B[0] Cb[1]/B[1] Cb[2]/B[2] Cb[3]/B[3] Cb[4]/B[4] Cb[5]/B[5] Cb[6]/B[6] Cb[7]/B[7] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] YCbCr 4:4:4 Cb[0] Cb[1] Cb[2] Cb[3] Cb[4] Cb[5] Cb[6] Cb[7] 4 : 2 : 2 (semi-planar) Y0[0] Y0[1] Y0[2] Y0[3] Cb[0] Cb[1] Cb[2] Cb[3] Y1[0] Y1[1] Y1[2] Y1[3] Cr[0] Cr[1] Cr[2] Cr[3] 4 : 2 : 2 (ITU656-like)[1] Cb[0] Cb[1] Cb[2] Cb[3] L L L L Y0[0] Y0[1] Y0[2] Y0[3] L L L L Cr[0] Cr[1] Cr[2] Cr[3] L L L L Y1[0] Y1[1] Y1[2] Y1[3] L L L L
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Table 26. Input pins
Input format ...continued Signal RGB 4:4:4 YCbCr 4:4:4 Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Cr[0] Cr[1] Cr[2] Cr[3] Cr[4] Cr[5] Cr[6] Cr[7] 4 : 2 : 2 (semi-planar) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Cb[10] Cb[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] 4 : 2 : 2 (ITU656-like)[1] Cb[4] Cb[5] Cb[6] Cb[7] Cb[8] Cb[9] Cb[10] Cb[11] L L L L L L L L Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] L L L L L L L L Cr[4] Cr[5] Cr[6] Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] L L L L L L L L Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] L L L L L L L L
Video port B VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] Video port C VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7]
[1]
Y[0]/G[0] Y[1]/G[1] Y[2]/G[2] Y[3]/G[3] Y[4]/G[4] Y[5]/G[5] Y[6]/G[6] Y[7]/G[7] Cr[0]/R[0] Cr[1]/R[1] Cr[2]/R[2] Cr[3]/R[3] Cr[4]/R[4] Cr[5]/R[5] Cr[6]/R[6] Cr[7]/R[7]
G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7]
L stands for tying to LOW voltage recommendation, e.g. ground.
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HDMI 1.3 transmitter with 1080p upscaler embedded
13.2 Timing parameters for supported video
The TDA9984A supports all EIA/CEA-861B standards and ATSC video input formats.
Table 27. Format Timing parameters for EIA/CEA-861B Format V frequency H total V total (Hz) 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 800 858 1650 2200 1716 1716 1716 3452 3452 3452 1716 2200 800 858 1650 2200 1716 1716 1716 3452 3452 3452 1716 2200 864 1980 2640 1728 1728 1728 1728 3456 3456 3456 525 525 750 1125 525 262 263 525 262 263 525 1125 525 525 750 1125 525 262 263 525 262 263 525 1125 625 750 1125 625 312 313 314 625 312 313 H frequency (kHz) 31.469 31.469 44.955 33.716 15.734 15.734 15.734 15.734 15.734 15.734 31.469 67.432 31.500 31.500 45.000 33.750 15.750 15.750 15.750 15.750 15.750 15.750 31.500 67.500 31.250 37.500 28.125 15.625 15.625 15.625 15.625 15.625 15.625 15.625 Pixel frequency (MHz) 25.175 27.000 74.175 74.175 27.000 27.000 27.000 54.000 54.000 54.000 54.000 148.350 25.200 27.027 74.250 74.250 27.027 27.027 27.027 54.054 54.054 54.054 54.054 148.50 27.000 74.250 74.250 27.000 27.000 27.000 27.000 54.000 54.000 54.000 Pixel repetition 1 1 1 1 2 2 2 4[1] 4[1] 4[1] 2 1 1 1 1 1 2 2 2 4[1] 4[1] 4[1] 2 1 1 1 1 1 2 2 2 4[1] 4[1] 4[1] Scaler
59.94 Hz systems 1 (VGA) 2, 3 4 5 6, 7 (NTSC) 8, 9 8, 9 10, 11 12, 13 12, 13 14, 15 16 1 (VGA) 2, 3 4 5 6, 7 (NTSC) 8, 9 8, 9 10, 11 12, 13 12, 13 14, 15 16 17, 18 19 20 21, 22 (PAL) 23, 24 23, 24 23, 24 25, 26 27, 28 27, 28
TDA9984A_4
640 x 480p 720 x 480p 1280 x 720p 1920 x 1080i 1440 x 480i 1440 x 240p 1440 x 240p 2880 x 480i 2880 x 240p 2880 x 240p 1440 x 480p
X X X X X X X X X X X X -
1920 x 1080p 59.9401 640 x 480p 720 x 480p 1280 x 720p 1920 x 1080i 1440 x 480i 1440 x 240p 1440 x 240p 2880 x 480i 2880 x 240p 2880 x 240p 1440 x 480p 60.000 60.000 60.000 60.000 60.000 60.000 60.000 60.000 60.000 60.000 60.000
60 Hz systems
1920 x 1080p 60.000 720 x 576p 1280 x 720p 1920 x 1080i 1440 x 576i 1440 x 288p 1440 x 288p 1440 x 288p 2880 x 576i 2880 x 288p 2880 x 288p 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000
50 Hz systems
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Table 27. Format 27, 28 29, 30 31
[1]
Timing parameters for EIA/CEA-861B ...continued Format 720 x 288p 1440 x 576p V frequency H total V total (Hz) 50.000 50.000 3456 1728 2640 314 625 1125 H frequency (kHz) 15.625 31.250 56.250 Pixel frequency (MHz) 54.000 54.000 148.50 Pixel repetition 4 2 1 Scaler -
1920 x 1080p 50.000
The format can also be defined with a repetition factor of up to 10.
Table 28. Standard
Timing parameters for ATSC DTV standards, which are not defined in EIA/CEA-861B Format V frequency H total V total (Hz) 30.000 29.970 25.000 23.976 3300 3300 3960 4125 750 750 750 750 H frequency Pixel frequency (kHz) (MHz) 22.500 22.478 18.750 17.982 74.250 74.175 74.250 74.175 Pixel repetition 1 1 1 1 Scaler -
SMPTE-296M 1280 x 720p
Table 29. Standard
Timing parameters for PC standards below 165 MHz Format 640 x 350p 640 x 400p 720 x 400p V frequency H total V total (Hz) 85.080 85.080 85.039 59.9401 72.809 75.000 85.008 832 832 936 800 832 840 832 1024 1056 1040 1056 1048 1344 1328 1312 1376 1264 1600 1576 1800 1728 1688 1688 445 445 446 525 525 500 520 625 628 666 625 631 806 806 800 808 817 900 907 1000 1011 1066 1066 H frequency Pixel frequency (kHz) (MHz) 37.861 37.861 37.937 31.469 37.861 37.500 43.269 35.156 37.879 48.077 46.875 53.673 48.362 56.476 60.023 68.677 35.522 67.500 77.094 60.000 85.937 63.981 79.977 31.500 31.500 35.500 25.175 31.500 31.500 36.000 36.000 40.000 50.000 49.500 56.250 65.000 75.000 78.750 94.500 44.900 108.000 121.500 108.000 148.450 108.000 135.000 Pixel repetition 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Scaler -
VGA
640 x 480p
SVGA
800 x 600p
56.250 60.317 72.188 75.000 85.061
XGA
1024 x 768p
60.004 70.069 75.029 84.997
1024 x 768i 1152 x 864p 1280 x 960p SXGA 1280 x 1024p
86.957 75.000 85.000 60.000 85.002 60.002 75.025
TDA9984A_4
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14. Package outline
HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad SOT841-4
c y exposed die pad X
Dh 60 61 41 40 ZE
A
e Eh w bp
M
E
HE
A A2
(A 3) A1 detail X L Lp
pin 1 index 80 1 w D HD
M
21 20 ZD B v
M
v
M
A
e
bp
B
0 DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 12.1 11.9 Dh 4.79 4.69 E (1) 12.1 11.9 Eh 4.79 4.69
5 scale
10 mm
e 0.5
HD
HE
L 1
Lp 0.75 0.45
v 0.2
w 0.08
y 0.1
ZD(1) ZE(1) 1.45 1.05 1.45 1.05
7 0
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION SOT841-4 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 06-04-25 06-06-20
Fig 18. Package outline SOT841-4 (HTQFP80)
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15. Abbreviations
Table 30. Acronym ACR AV CMOS CTS CTS/N DDC DE DTS DTV DVD DVI EAV EDID E-EDID FREF HBR HD HDCP HDMI HDTV HREF HSYNC KSV LSB LV-TTL MSB NTSC OTP PAL PCM PLL SAV SHA-1 S/PDIF TMDS VHREF VREF VSYNC YCbCr
TDA9984A_4
Abbreviations Description Audio Clock Recovery Audio Video Complementary Metal-Oxide Semiconductor Clock Time Stamp Clock Time Stamp integer divider Display Data Channel Data Enable Digital Transmission System Desk Top Video Digital Versatile Disc Digital Visual Interface End Active Video Extended Display Identification Data Enhanced Extended Display Identification Data Field REFerence High Bit Rate High Definition High-bandwidth Digital Content Protection High-Definition Multimedia Interface High-Definition Television Horizontal REFerence Horizontal SYNChronization Key Selection Vector Least Significant Bit Low Voltage Transistor-Transistor Logic Most Significant Bit National Television System Committee One Time Programming Phase Alternated Line Pulse Code Modulation Phase-Locked Loop Start Active Video Secure Hash Algorithm 1 Sony/Philips Digital Interface Transition Minimized Differential Signalling Vertical Horizontal REFerence Vertical REFerence Vertical SYNChronization Y = luminance, Cb = Chroma component blue, Cr = Chroma component red
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
37 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
16. Revision history
Table 31. Revision history Release date 20090115 Data sheet status Product data sheet Change notice Supersedes TDA9984A_3 Document ID TDA9984A_4 Modifications:
* * * * * * * * * * *
All document: changed Y-CB-CR in YCbCr, CB in Cb and CR in Cr for consistency Section 1: rewritten the first sentence Section 2: added "Dolby-True HD and DTS-HD" Figure 1, Figure 2 and Table 3: updated the pins 15, 16 and 45: name and description Table 1: added the row VDDA(PLL)(1V8) Section 8.2: changed the reference HDMI 1.2a in 1.3 and in the table 15, added the column HBR Section 8.2.2: updated the input clock with a frequency at 64fs Section 8.2.3: added this paragraph High bit rate audio Table 22: updated Table 25: added the part HBR mode Table 1, Table 20, Table 22, Table 23, Table 24 and Table 25: changed the temperature min 0 C to -5 C and temperature max 70 C to +85 C Product data sheet Preliminary data sheet Objective data sheet TDA9984A_2 TDA9984_1 -
TDA9984A_3 TDA9984A_2 TDA9984_1
20080410 20080115 20070723
TDA9984A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
38 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
17.4 Licenses
Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org.
17.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA9984A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 15 January 2009
39 of 40
NXP Semiconductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
19. Contents
1 2 3 4 5 6 7 7.1 8 8.1 8.1.1 8.1.2 8.1.2.1 8.1.2.2 8.1.2.3 8.1.2.4 8.1.2.5 8.1.2.6 8.1.2.7 8.1.2.8 8.1.3 8.1.3.1 8.1.3.2 8.1.4 8.1.5 8.1.5.1 8.1.5.2 8.1.6 8.1.7 8.1.8 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.1.1 8.3.1.2 8.4 8.4.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 8 Video processing . . . . . . . . . . . . . . . . . . . . . . . 8 Internal assignment . . . . . . . . . . . . . . . . . . . . . 8 Input format mappings . . . . . . . . . . . . . . . . . . . 9 RGB 4 : 4 : 4 external sync input (rising edge) 11 YCbCr 4 : 4 : 4 external sync input (rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 YCbCr 4 : 2 : 2 ITU656-like external sync input (rising edge) . . . . . . . . . . . . . . . . . 13 YCbCr 4 : 2 : 2 ITU656-like external sync input (rising and falling) . . . . . . . . . . . . . 14 YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising edge) . . . . . . . . . . . . . . . . . 15 YCbCr 4 : 2 : 2 ITU656-like embedded sync input (rising and falling) . . . . . . . . . . . . . 16 YCbCr 4 : 2 : 2 semi-planar external input (rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 YCbCr 4 : 2 : 2 semi-planar embedded sync input (rising edge) . . . . . . . . . . . . . . . . . 18 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 19 Timing extraction generator . . . . . . . . . . . . . . 19 Data enable generator . . . . . . . . . . . . . . . . . . 19 Input and output video format . . . . . . . . . . . . . 19 Scaler unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Scaler features . . . . . . . . . . . . . . . . . . . . . . . . 19 Input and output video scaler . . . . . . . . . . . . . 20 Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Color space converter. . . . . . . . . . . . . . . . . . . 21 Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 21 Audio processing . . . . . . . . . . . . . . . . . . . . . . 21 S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 High bit rate audio. . . . . . . . . . . . . . . . . . . . . . 23 HDCP processing . . . . . . . . . . . . . . . . . . . . . . 23 High-bandwidth digital content protection. . . . 23 Repeater function . . . . . . . . . . . . . . . . . . . . . . 23 SHA-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TMDS serializer . . . . . . . . . . . . . . . . . . . . . . . 23 RxSense detection . . . . . . . . . . . . . . . . . . . . . 23 8.4.2 8.4.3 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.6 8.6.1 8.6.2 8.6.2.1 8.6.2.2 8.7 9 9.1 9.2 10 11 12 13 13.1 13.2 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 TMDS output buffers . . . . . . . . . . . . . . . . . . . Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . Control blocks. . . . . . . . . . . . . . . . . . . . . . . . . Clock management . . . . . . . . . . . . . . . . . . . . Interrupt controller . . . . . . . . . . . . . . . . . . . . . Hot plug detection . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . Power management . . . . . . . . . . . . . . . . . . . . DDC-bus interface . . . . . . . . . . . . . . . . . . . . . DDC-bus channel . . . . . . . . . . . . . . . . . . . . . . E-EDID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-EDID reading . . . . . . . . . . . . . . . . . . . . . . . HDMI and DVI receiver discrimination . . . . . . I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . I2C-bus registers definitions . . . . . . . . . . . . . Memory page management . . . . . . . . . . . . . . ID version . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Input format . . . . . . . . . . . . . . . . . . . . . . . . . . Timing parameters for supported video . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 25 25 25 26 26 26 27 27 27 27 27 27 28 28 28 28 29 29 29 31 32 34 36 37 38 39 39 39 39 39 39 39 40
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 January 2009 Document identifier: TDA9984A_4

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